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With the development of communication systems and the construction of data centers, 100 Gbit/s (hereinafter referred to as 100G) Ethernet has begun to be commercialized. In September 2018, IEEE released the 802.3cd protocol to formulate the standard for 100G Ethernet. In fact, the market demand for 100G has even appeared before the standard. The 100G QSFP28 CWDM4 optical transceiver module is a 100G Ethernet client-side optical module. It has broad application prospects because of its high integration, hot-swappable support, fast speed, small size, and relatively mature technical solutions. This paper presents a 100G QSFP28 CWDM4 design scheme that conforms to the IEEE 802.3cd standard and receives COB (Chip-on-Board Package) technology, and verifies the feasibility of its application by testing various parameters of the optical module.

1. Overall design of optical module

The optical module introduced in this article is a relatively mainstream optical module in the market with MCU (single chip microcomputer) as the control core and Driver (driver) as the light-emitting drive. Its overall design idea is as follows: Through the electrical interface, the signal enters the module PCB in the form of electricity, and after being identified and processed by the chip and the single-chip microcomputer, four channels of light are sent out through the DML (directly modulated laser) at the transmitting end. The center wavelengths are respectively 1271 nm, 1291 nm, 1311 nm, 1331 nm, and finally the optical path is synthesized by MUX into one optical coupling into SMF for export and transmission; when the optical signal is received at the receiving end, it passes through DE-MUX (optical splitter ) for light splitting, and one path of light is divided into four paths of light with center wavelengths of 1271 nm, 1291 nm, 1311 nm, and 1331 nm, and then stimulated by PD (photodiode) to convert the optical signal into a weak electrical signal, and finally through the TIA (Transimpedance amplifier) linearly amplifies the electrical signal, transmits it to the optical module circuit board, and processes it by the receiving chip. The simple function block diagram of its module is shown in Figure 1.

The CWDM4 module is connected to the outside by two interfaces, in which the electrical signal is connected to the host through a 38PIN gold finger to complete the power supply, control, communication, etc. of the module, and the optical signal is input and output through a pair of LC optical interfaces. The block diagram of the hardware principle is shown in Fig. 2 .

Inside the module, the MCU completes the initial setting of the module, and its work includes responding to the content stipulated in the SFF-8636 protocol, monitoring the working status of the module, and automatically adjusting the working parameters of the module. The LD Driver in the module is used to complete the input of self-bias differential, integrated programmable equalization processing, realization of limiting amplifier circuit, optional function of clock data recovery and retiming, and LD driver. The Receiver in the module has a built-in PD bias circuit, integrated transimpedance amplification, automatic gain amplification, and limiting amplifier circuit. Clock data recovery and retiming functions are optional, and functions such as de-emphasis/equalization configuration can be realized.